DDR (double data rate) semiconductor devices are widely used as main memory for computer systems and other data devices. DDR memory devices are so named because they are capable of outputting two-bits of data in a single clock period, using a single data input/output pin. With the spread of DDR semiconductor devices, the operating frequency of devices has been increased.
Since present high-speed graphic memories require a minimal operational speed of about 500 MHz, a four-bit pre-fetch method has been widely adopted over the conventional two-bit pre-fetch method. Correspondingly, the number of CAS (Column Access Strobe) latencies in memories has increased. For the convenience of explanation, when the number of CAS latencies is n (where n is a positive integer number), it will be expressed as ‘CL=n.’
tCK is a unit used to measure clock cycles. In general, in a four-bit pre-fetch type memory, four bits of data are input or output through one data input/output pin in two tCKs. In addition, since a column selection line (CSL) is activated over a period of two clock cycles in the four-bit pre-fetch type memory, it is possible to issue a read command every two clock cycles. Accordingly, a minimum time gap (referred to as tCCD) between two read commands is two tCKs.
As described above, since the number of CSLs and a period of time during which a CSL is activated have increased, core timing, i.e., the time between when a CSL is activated and when data are developed by a data sense amplifier, does not lead to a serious problem in a high-speed device having a speed of 500 MHz or greater. More important than core timing, in forming a high-frequency device, is a data input/output element in a semiconductor device.
A “wave-pipeline” type data output circuit has been widely used to make high-speed memories with long latency. The number of latches per bit of data that is necessary to constitute a pipeline in such a wave-pipeline type data output circuit is represented by an integer value that is equal to, or the next integer larger than ‘a maximum number of latencies/tCCD.’ Accordingly, when a maximum number of latencies is 6, three latches are required for each bit. When a maximum number of latencies is 7, four latches are required for each bit. Since four data elements are output through a data input/output pin in response to one read command in a four-bit pre-fetch type memory, 12 latches are required for each data input/output pin when the maximum number of latencies is 6. Similarly, when a maximum number of latencies is 7, the number of latches required for each data input/output pin is 16.
FIG. 1 is a diagram illustrating a conventional data output circuit of a DDR semiconductor device. A data output circuit 100 is a wave-pipeline type data output circuit that adopts a four-bit pre-fetch method and satisfies the following conditions: CL=6 and tCCD=2 tCKs.
The data output circuit 100 includes twelve latches 111˜122 and an output data buffer 140. For the convenience of explanation, a bitline sense amplifier B/L S/A, a data sense amplifier DATA S/A, and a burst data ordering unit 200 are shown in FIG. 1 together with the data output circuit 100.
When a wordline is activated, data stored in a memory cell are conveyed by a bitline (not shown) and are sensed and amplified by the bitline sense amplifier B/L S/A.
Data corresponding to an activated CSL among the data sensed by the bitline sense amplifier B/L S/A are transmitted to the data sense amplifier DATA S/A and amplified. Here, since the data output circuit 100 adopts a four-bit pre-fetch method, four column selection lines (CSL1-CSL4) are activated at the same time in response to one read command.
The data of the bitline sense amplifier B/L S/A corresponding to the activated CSL are developed by the data sense amplifier DATA S/A, are arranged in an appropriate order by the burst data ordering unit 200, and are simultaneously input into four of the twelve latches 111˜122 by operation of one of the three switches DL1, DL2, or DL3.
The data output circuit 100 shown in FIG. 1 multiplexes data output from the latches 111˜122 so that even-numbered data are multiplexed separately from odd-numbered data and then outputs the results of the multiplexing. The even-numbered data are output in response to rising edges of a clock, and the odd-numbered data are output in response to falling edges of the clock.
FIG. 2 is a diagram illustrating the output timing of the conventional data output circuit 100 shown in FIG. 1. The operation of the conventional data output circuit 100 will be described in the following with reference to FIGS. 1 and 2.
Four data SDIOF1, SDIOF2, SDIOS1, and SDIOS2 simultaneously output from the burst data ordering unit 200 are sequentially input into latches of their corresponding bits. The first datum SDIOF1 is input into a single latch among the first through third latches 111˜113, the second datum SDIOF2 is input into a single latch among the fourth through sixth latches 114˜116, the third datum SDIOS1 is input into a single latch among the seventh through ninth latches 117˜119, and the fourth datum SDIOS2 is input into a single latch among the tenth through twelfth latches 120˜122. Which latches the first through fourth data SDIOF1, SDIOF2, SDIOS1, and SDIOS2 are respectively input into is controlled by input control signals DLj (j is between 1 and 3).
Even-numbered output control signals CDQFj (j is between 1 and 6) and odd-numbered output control signals CDQSj (j is between 1 and 6) determine a latch the data of which will be output to an even-numbered node DOFi and an odd-numbered node DOSi.
The data output from the first through sixth latches 111˜116 are output to the even-numbered node DOFi when their corresponding even-numbered output control signal CDQFj (j between 1 and 6) is activated. The data output from the seventh through twelfth latches 117˜122 are output to the odd-numbered node DOSi when their corresponding odd-numbered output control signal CDQSj (between 1 and 6) is activated. The data output to the even-numbered node DOFi and the odd-numbered node DOSi are sequentially latched by a latch 130, and are output to the outside of the DDR semiconductor device via the output data buffer 140.
The output data buffer 140 generally includes a pull-up transistor TP and a pull-down transistor TN. The pull-up transistor TP and the pull-down transistor TN each drive an output signal DOUT at either a power supply voltage or a ground voltage in response to output data DO of the latch 130.
Referring to FIG. 2, four output control signals CDQF1, CDQS1, CDQF2, and CDQS2 are sequentially activated at intervals of half a clock cycle, i.e., at intervals of tCK/2. Then, and in sequence controlled by CDQF1, CDQS1, CDQF2, and CDQS2, respectively, the datum contained in the first latch 111 is output to the even-numbered node DOFi, the datum contained in the seventh latch 117 is output to the odd-numbered node DOSi, the datum contained in the fourth latch 114 is output to the even-numbered node DOFi, and the datum contained in the tenth latch 120 is output to the odd-numbered node DOSi. The data output circuit 100 shown in FIG. 1 needs 12 output control signals (CDQF1, CDQS1, CDQF2, and CDQS2 for each of the timing signals DL1, DL2, and DL3) generated at intervals of tCK/2, so as to correctly output the data of each of the latches 111˜122 as DDR data.
If a maximum number of latencies in a semiconductor memory device is 7, the number of latches is increased to 16, and the semiconductor memory device needs 16 different output control signals. Because of the high operational frequencies involved, controlling so many output control signals in a short time becomes problematic.
Thus, in conventional circuits, as the operational frequency of a semiconductor device increases, in other words, as tCK decreases, it becomes more difficult to control skews among the output control signals. In addition, conventional data output circuits tend to generate a considerable number of output control signals. Moreover, since it is very complex to transmit such output control signals to a pipeline circuit of the data output circuit, it is difficult to control data output.
Embodiments of the invention address this and other limitations in the prior art.